An integrated circuit is an interconnected ensemble of devices formed within a semiconductor material and within a dielectric material that overlies a surface of the semiconductor material. Devices that may be formed within the semiconductor include MOS transistors, bipolar transistors, diodes, and diffused resistors. Devices that may be formed within the dielectric include thin film resistors and capacitors. The devices are interconnected by conductor paths formed within the dielectric. Typically, two or more levels of conductor paths, with successive levels separated by a dielectric layer, are employed as interconnections. In current practice, copper and silicon oxide are typically used for, respectively, the conductor and the dielectric.
The deposits in a copper interconnect typically include a dielectric layer, a barrier layer, a seed layer, copper fill, and a copper cap. Conventional electrochemical deposition (ECD) for copper fill and cap is performed in the feature using an acid plating chemistry. Electrochemical deposition of copper has been found to be the most cost effective manner by which to deposit a copper metallization layer. In addition to being economically viable, such deposition techniques provide a substantially bottom up (e.g., non-conformal) copper fill that is mechanically and electrically suitable for interconnect structures.
Conventional ECD copper acid plating chemistry may include, for example, copper sulfate, sulfuric acid, hydrochloric acid, and organic additives (such as accelerators, suppressors, and levelers). The additives drive void-free, bottom-up fill in a feature through their adsorptive and desorptive properties and through competitive reactions, for example, by suppressing plating at the top and on the sidewalls of the feature, while enhancing plating at the bottom of the feature.
The steady downscaling of interconnect features presents new challenges, because the characteristic dimensions (such as feature width and aspect ratio) hinder and alter the reactivity characteristics of additives typically used. In that regard, sub-30 nm features used for copper interconnects have small enough volume and require such few copper atoms that, in a conventional ECD copper acid plating chemistry, the features become filled within the first few seconds of plating. This is a shorter time period than that required for the adsorption and desorption kinetics of the bath additives that drive traditional bottom-up filling.
Therefore, in small features (e.g., sub-30 nm features), a conventional ECD fill may result in a lower quality interconnect due to the presence of voids. As one example of a type of void formed using conventional ECD deposition, the opening of the feature may pinch-off. Many other types of voids can also result from using the conventional ECD copper fill process in a small feature. Such voids and other intrinsic properties of a deposit formed using conventional ECD copper fill can increase the resistance of the interconnect, thereby slowing the device and deteriorating the reliability of the copper interconnect.
Therefore, there exists a need for methods of electrochemical deposition for filling sub-30 nm features from the bottom up, leaving a reduced number of void regions. Embodiments of the present disclosure are directed to filling this and other needs.